Multilayer Layer Graphene Nanoribbon Flash Memory: Analysis of Programming and Erasing Operation

Flash memory based on floating gate transistor is the most widely used memory technology in modern microelectronic applications. We recently proposed a new concept of multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT) based floating gate transistor design for future nanoscale flash memory technology. In this paper, we analyze the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. We anticipate that the proposed floating gate transistor would adopt Fowler-Nordheim (FN) tunneling during its programming and erase operations. In this paper, we have investigated the mechanism of tunneling current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that FN tunneling is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide.Comment: in IEEE SOCC, Las Vegas, USA, 201

An improved extrinsic monolingual plagiarism detection approach of the Bengali text

Plagiarism is an act of literature fraud, which is presenting others’ work or ideas without giving credit to the original work. All published and unpublished written documents are under the cover of this definition. Plagiarism, which increased significantly over the last few years, is a concerning issue for students, academicians, and professionals. Due to this, there are several plagiarism detection tools or software available to detect plagiarism in different languages. Unfortunately, negligible work has been done and no plagiarism detection software available in the Bengali language where Bengali is one of the most spoken languages in the world. In this paper, we have proposed a plagiarism detection tool for the Bengali language that mainly focuses on the educational and newspaper domain. We have collected 82 textbooks from the National Curriculum of Textbooks (NCTB), Bangladesh, scrapped all articles from 12 reputed newspapers and compiled our corpus with more than 10 million sentences. The proposed method on Bengali text corpus shows an accuracy rate of 97.31

Analysis of radiation effect on the threshold voltage of flash memory device

Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The the operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this letter, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model

Collapsible Tabular Visualization of Aspects in Object Oriented Programming

Due to its implicit invocation nature ofAspect Oriented Programming (AOP), locating a jointpoint for executing aspect is extremely difficult. Hence,it becomes difficult to understand the application’sflow and behavior. Current AOP visualization tools havelimitations such as high dependency on other tools,confusing and excessive use of color to represent aspectsand using an outdated version of AspectJ. In thispaper, we propose a new approach collapsibletabular visualization tool to visualize and represent AOPfeatures to aid the programmers in betterunderstanding AOP applications. We have come outof traditional color-based aspect visualization and developeda web based tool: AspectViz that visualizes the aspects ina simple collapsible table. A questionnaire containingfour different questions related to aspects visualizationwas developed to compare AspectViz with currentvisualization tools. 20 graduate students andprofessional software developers were invited to participatein the test experiment as well as the survey. We havecompared its performance with existing AOPvisualization tools i.e. the AJDT and the AspectMaps andshowed how it outperformed in many cases, which is nocolor confusion, simple tabular visualization of aspects, nodependency on third-party software, easy to understand andthe time it took to find a particular aspect was less etc.Collapsible tabular visualization enhanced the usability andperformance of aspect locating in aspect-orientedprogramming

Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits

Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analyses are done based on the equivalent capacitance model of the device. We have analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide. With the growing demand for nonvolatile flash memory devices and increasing limitations of silicon technologies, there has been a growing interest to develop emerging flash memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide. In this paper, we have presented detail analysis of the electrical properties and performance characteristics of the proposed FGT device. We have focused on the following aspects: current voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and reading power consumptions compared to the existing FGTs, and layer-by-layer current voltage characteristics comparison of the proposed GFGT device. To realize graphene field effect transistor (GFET), a general model is developed, validated and analyzed. This model is also used to estimate graphene channel behavior of the proposed GFGT. Reliability is the major concern of the Flash memory technology. We have analyzed retention characteristics of the proposed GFGT. We also have developed a radiation harness test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model. Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the promising future logic devices. Many other nanoelectronic devices based on MoS2 are currently under investigation. However, the challenge of providing reliable and efficient contact between 2D materials like MoS2 and the metal is still unresolved. The contact resistance between metal and MoS2 limits the application of MoS2 in current semiconductor technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented. Specific contributions of this work are:investigation of the physical, material and electrical parameters that would determine the contact properties, analysis of the combined impact of the top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters, such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer length (LT), investigation of the ways to incorporate the developed contact model into the electronic design automation (EDA) tools and investigation of different contact materials for the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when minimum spacing interconnects are used. The major contributions of this research work are as follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and verification. Therefore, a solid CAD solution is provided here. Compatible with 40nm-technology design, which enables the Silicon Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best knowledge, at the interposer level, this design reports the most dense and well-defined RDL, TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor

DPCSpell: A Transformer-based Detector-Purificator-Corrector Framework for Spelling Error Correction of Bangla and Resource Scarce Indic Languages

Spelling error correction is the task of identifying and rectifying misspelled words in texts. It is a potential and active research topic in Natural Language Processing because of numerous applications in human language understanding. The phonetically or visually similar yet semantically distinct characters make it an arduous task in any language. Earlier efforts on spelling error correction in Bangla and resource-scarce Indic languages focused on rule-based, statistical, and machine learning-based methods which we found rather inefficient. In particular, machine learning-based approaches, which exhibit superior performance to rule-based and statistical methods, are ineffective as they correct each character regardless of its appropriateness. In this work, we propose a novel detector-purificator-corrector framework based on denoising transformers by addressing previous issues. Moreover, we present a method for large-scale corpus creation from scratch which in turn resolves the resource limitation problem of any left-to-right scripted language. The empirical outcomes demonstrate the effectiveness of our approach that outperforms previous state-of-the-art methods by a significant margin for Bangla spelling error correction. The models and corpus are publicly available at https://tinyurl.com/DPCSpell.Comment: 23 pages, 4 figures, and 7 table

Analytical Hierarchy Process (AHP) Approach on Consumers’ Preferences for Selecting Telecom Operators in Bangladesh

This study is designed for the analysis of the consumers’ preferences for selecting the telecom operators in Bangladesh. This study includes an empirical analysis using AHP model based on some criteria of consumers’ preferences. This study provides relevant ranking using AHP model rather than finding the causal relationship among the variables. The results of the empirical analysis shows that the respondents preferred the network criterion as most important criterion for their preferences, and also preferred two telecom operators Grameen Phone and Airtel under different criteria. Finally, the global weights of the AHP analysis show that the respondents preferred Grameen Phone most than all other telecom operators in Bangladesh. Keywords: AHP Analysis, Telecom Operators, Consumers’ Satisfaction